1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a structure of a circuit for adjusting an output slew rate of a data output circuit. More specifically, the present invention relates to a structure for adjusting an output slew rate of a data output circuit in a clock synchronous semiconductor memory device, which in turn outputs data in synchronization with a clock signal.
2. Description of the Background Arts
In recent years, a clock synchronous semiconductor memory device, which transfers data in synchronization with a clock signal such as a system clock, has been used for transferring data fast. The clock synchronous semiconductor memory device takes in an external control signal, an address signal and write data in synchronization with a clock signal, and transfers output data in synchronization with the clock signal. Therefore, the control signal and the address signal can be taken in with only a skew of the external signals with respect to the clock signal considered, to start the internal operation at a faster timing.
Further, the data is transferred in synchronization with the clock signal. Therefore, the data transfer rate is equivalently equal to the rate of clock signal so that the data can be transferred at a high rate.
FIG. 14 schematically shows a structure of a clock synchronous semiconductor memory device in the prior art. In FIG. 14, the semiconductor memory device includes: an internal memory circuitry 900 which has a plurality of memory cells, and reads out data of a selected memory cell in accordance with a clock signal CLK and an output enable signal OE for producing internal read data IQ; and an output circuit 902 which externally transfers internal read data in synchronization with clock signal CLK for producing output data Q.
Internal memory circuitry 900 includes a memory cell array, a memory row select circuit, a memory cell select circuit, an internal data write circuit, an internal data read circuit, an address buffer circuit and others.
FIG. 15 is a timing chart representing a data output operation of the semiconductor memory device shown in FIG. 14. As shown in FIG. 15, internal read data IQ is produced from internal memory circuitry 900 in accordance with output enable signal OE and clock signal CLK. FIG. 15 shows internal read data IQ0 and IQ1 changing in synchronization with rising of clock signal CLK.
Output circuit 902 transfers internal read data IQ read from internal memory circuit 900 in synchronization with the falling of clock signal CLK. Output data Q, which is externally read out, changes in synchronization with falling of clock signal CLK. An external logic circuit such as a processor samples the received data in synchronization with the rising of dock signal CLK. The dock signal CLK is a clock signal synchronized with, e.g., an external system clock.
In FIG. 15, output circuit 92 is shown producing output data Q in synchronization with the falling of clock signal CLK. However, output circuit 902 may produce output data Q in synchronization with both the rising and falling edges of clock signal CLK. Further, output circuit 902 may output data Q in synchronization with the rising of clock signal CLK (internal read data IQ is transferred in synchronization with the falling of clock signal CLK).
As described above, the output data is transferred in synchronization with clock signal CLK, and a logic such as an external processor can accurately sample the data by sampling the data in synchronization with clock signal CLK, so that a memory system capable of fast data transfer can be implemented.
In the structure of the synchronous semiconductor memory device, which transfers output data Q in synchronization with clock signal CLK, output circuit 902 is required to drive the output node fast if clock signal CLK is a fast clock signal.
When a semiconductor memory device is housed in a package, a pad and a bonding wire are usually connected to an output node, and a large inductance component is present at the output node. Therefore, as shown in FIG. 16, when the output node is driven fast, ringing may occur. If a ringing is caused and the ringing following an overshoot at the rising of output data Q has a large amplitude, an error may occur in determination of H- and L-levels of the data. Likewise, the ringing following undershoot at the falling of data Q may cause a similar error in determination of H- and L-levels of data Q. During continuation of the above ringing, or for time periods Ta and Th, the determination of the logical level of data cannot be performed, and fast data reading cannot be performed. For preventing the above problem related to the ringing, a way of driving the output node in multiple stages has been employed to suppress the ringing conventionally, as described below.
FIG. 17 shows, by way of example, a structure of output circuit 902 shown in FIG. 14. In FIG. 17, output circuit 902 includes: a transmission gate 902a which transmits internal read data IQ in accordance with complementary clock signals CLK and /CLK; a buffer circuit 902b which buffers the output signal of transmission gate 902a to produce a drive signal (internal data read signal) q; an N-channel MOS transistor TR1 which discharges output node 904 to the ground voltage level in accordance with drive signal q received from buffer circuit 902b; a transmission gate 902c which passes internal read data IQ in accordance with complementary delayed clock signals CLKd and /CLKd; a buffer circuit 902d which buffers the output signal of transmission gate 902c to produce a delayed drive signal qd; and an N-channel MOS transistor TR2 which discharges output node 904 to the ground voltage level in accordance with delayed drive signal gd received from buffer circuit 902d. 
Output node 904 is pulled up to an H-level voltage by a pull-up resistance, which is externally provided to an output signal line (output data line), but is not shown. Output circuit 902 drives output node 904 with an open drain structure.
Transmission gates 902a and 902c are rendered conductive in a same phase but in a phase-shifted timing relationship.
Each of buffer circuits 902b and 902d includes cascaded two inverter circuits, and buffers the received signal for producing drive signal q or qd. Delayed clock signal CLKd is produced by delaying clock signal CLK with a slew rate adjusting circuit, which will be described later.
FIG. 18 is a signal waveform diagram representing, by way of example, an operation of output circuit 902 shown in FIG. 17. In the example shown in FIG. 18, when output circuit 902 is in the output high-impedance state, external data Q is pulled up to H-level, and internal read data IQ is at L-level in a standby state.
Internal read data IQ changes and rises to H-level in synchronization with the rising of clock signal CLK. Clock signals CLK and CLKd change in accordance with the internal clock signal when output enable signal OE is active.
When internal read data IQ rises from L-level to H-level, both clock signals CLK and CLKD are at H-level, and transmission gates 902a and 902c are both off so that output data Q is held at H-level.
When clock signal CLK falls to L-level, transmission gate 902a is rendered conductive, and drive signal q attains H-level in accordance with internal read data IQ so that MOS transistor TR1 is rendered conductive to discharge output node 904 to the ground voltage level. At this time point, transmission gate 902c is off, and MOS transistor TR2 maintains the off state. When a predetermined time elapses, delayed clock signal CLKd attains L-level, and transmission gate 902c is rendered conductive to set drive signal qd to H-level so that MOS transistor TR2 is turned on. Responsively, output node 904 is driven by two MOS transistors TR1 and TR2.
Thereafter, clock signal CLK rises to H-level, and transmission gate 902a is rendered non-conductive, and MOS transistor TR1 is turned off by a not shown circuit, and MOS transistor TR2 discharges output node 904 to the ground voltage level. When delayed clock signal CLKd attains H-level, transmission gate 902c is rendered non-conductive, and MOS transistor TR2 is likewise turned off by a circuit (not shown), so that output circuit 902 attains the output high-impedance state.
In the output circuit shown in FIG. 17, MOS transistor TR1 discharges output node 904. After elapsing of a predetermined time, MOS transistors TR1 and TR2 discharge output node 904 to the ground voltage level. Therefore, occurrence of the ringing can be suppressed without delaying the output timing (definite timing) of output data Q, because two MOS transistors TR1 and TR2 rapidly discharge output node 904 after the voltage on output node 904 lowers to a voltage level not causing ringing. Thus, the changing rate of output data Q on output node 904, or the output slew rate is adjusted to output the data rapidly and stably.
The speed or rate of driving output node 904 by MOS transistors TR1 and TR2, or the output slew rate depends on manufacturing process conditions, operation voltage conditions and operation temperature conditions. For example, if the size (ratio of channel width to channel length) of output driving MOS transistors TR1 and TR2 increases, MOS transistors TR1 and TR2 have increased current drive capabilities, and rapidly discharge output node 904 to the ground voltage level. In this case, it is necessary to increase the time length for driving the output node by one MOS transistor TR1 for preventing occurrence of the ringing. If the sizes of MOS transistors TR1 and TR2 decrease, the current drive capability for output node 904 decreases, so that both MOS transistors TR1 and TR2 are used for driving output node 904. Thereby, output node 904 is driven fast without causing the ringing.
When the power supply voltage rises, the gate voltages of MOS transistors TR1 and TR2 become high to rise the current drive capabilities of MOS transistors TR1 and TR2. When the operation temperature rises, the current drive capabilities of MOS transistors TR1 and TR2 rise. Therefore, the delay time of delayed clock signal CLKd must be adjusted in accordance with the manufacturing process conditions, operation temperature conditions and operation power supply voltage conditions for adjusting the time period, for which MOS transistors TR1 and TR2 are in a conductive state, in accordance with these conditions.
FIG. 19 shows, by way of example, the structure of a conventional slew rate adjusting circuit. In FIG. 19, the slew rate adjusting circuit includes: inverter circuits 910a and 910b that are connected in series between an input node 905 and an output node 907; tristate inverter buffers 912a and 912b which are connected in series between input node 905 and output node 907, and are selectively activated in accordance with slew rate adjusting data S1 and /S1; and tristate inverter buffers 914a and 914b which are connected in series between input and output nodes 905 and 907, and are selectively activated in accordance with slew rate adjusting data S0 and /S0.
Tristate inverter buffers 912a and 912b become inactive to be set to the output high-impedance state when slew rate adjusting data S1 is at L-level. Tristate inverter buffers 914a and 914b are set to the inactive state, and attains the output high-impedance state when slew rate adjusting data S0 is at L-level. Slew rate adjusting data S0 and /S0 are complementary to each other, and slew rate adjusting data S1 and /S1 are complementary to each other.
When slew data adjusting data S0 and S1 are both at L-level, tristate inverter buffers 912a, 912b, 914a and 914b are all in the output high-impedance state. In this state, delayed clock signal CLKd is produced by inverter buffers 910a and 910b. Therefore, the delay time of delayed clock signal CLKd with respect to clock signal CLK takes the largest value. This state corresponds to the state that the output circuit has a large output node drive capability, and the time period, for which one MOS transistor TR1 drives the output node, is increased.
When slew rate adjusting data S0 and S1 are set to H-level, all tristate inverter buffers 912a, 912b, 914a and 914b become active, and delayed clock signal CLKd is produced by these inverter buffer 910b and tristate inverter buffers 912b and 914. In this case, therefore, the size (current drive capability) of one inverter buffer equivalently increases so that the delay time of delayed clock signal CLKd with respect to clock signal CLK becomes short. Thus, the time period, for which two MOS transistors TR1 and TR2 drive the output node in the output circuit, is made long.
Thus, in the case where the current drive capability for the output node of output circuit is small, the delay time of delayed dock signal CLKd is set small, and the two MOS transistors are used for driving the output node fast.
As shown in FIG. 19, the size of the inverter buffer for producing delayed clock signal CLKd is equivalently increased in accordance with slew rate adjusting data S0 and S1, and thereby the delay time of delayed clock signal CLKd can be reduced.
The slew rate adjusting circuit shown in FIG. 19 is also provided for complementary clock signals /CLK and /CLKd.
FIG. 20 schematically shows, by way of example, a structure of a circuit for generating the slew rate adjusting data S0 and S1. In FIG. 20, the slew rate adjusting data generating circuit includes: a dummy P-channel MOS transistor 920 which is coupled to the power supply node; a current monitor circuit 921 which monitors the current flowing through dummy P-channel MOS transistor 920; a dummy N-channel MOS transistor 922 coupled to the ground node; a current monitor circuit 923 which is coupled between the power supply node and dummy N-channel MOS transistor 922, and monitors the current flowing through dummy N-channel MOS transistor 922; and a decode circuit 924 which decodes output signals Pmr and Nmr of current monitor circuits 921 and 923 for producing slew rate adjusting data S0 and S1.
Dummy P-channel MOS transistor 920 receives, on its gate, a reference voltage Va, and dummy N-channel MOS transistor 922 receives, on its gate, a reference voltage Vb. Reference voltages Vb and Va are set to such values that dummy transistors 920 and 922 have the gate-source voltages equal in absolute value to each other. Thus, a relationship of Va=Vddxe2x88x92Vb is satisfied.
These dummy transistors 920 and 922 are formed on the same chip with MOS transistors TR1 and TR2 included in output circuit 902, and are subject to the same variations in parameters, operation temperature and power supply voltage Vdd. as output circuit 902. The currents flowing through dummy MOS transistors 920 and 922 are monitored, and the current drive capability of the output node of output circuit 902 is detected. Current monitor circuits 921 and 923 detect the levels of the currents flowing through corresponding dummy MOS transistors 920 and 922, among discrete current levels (e.g., high, middle and low levels), and produce signals Pmr and Nmr in accordance with the result of detection.
If the current drive capability of the output node of output circuit 902 is large, the current drive capabilities of these dummy MOS transistors 920 and 922 are also large, and large currents flow through dummy MOS transistors 920 and 922, respectively. In this case, the delay time of the delayed clock signal is increased, and the time period for driving the output node by one MOS transistor is increased. Thus, the detection result data Pmr and Nmr are interrelated with the output node drive capability of the output circuit.
As described above, current monitor circuits 921 and 923 monitor the currents flowing through dummy MOS transistors 920 and 922, whereby the current drive capabilities of output driving MOS transistors TR1 and TR2 in output circuit 902 can be detected. Decoder 924 decodes detected result data Pmr and Nmr, to produce slew rate adjusting data S0 and S1.
The output node drive capability of the output circuit is monitored by utilizing the slew rate adjusting data producing circuit as shown in FIG. 20, whereby the output slew rate can be adjusted in accordance with the actual capability of this output circuit.
In the delay clock generating circuit, however, delay paths each including the same number of stages of inverter buffers are connected in parallel with each other. In accordance with slew rate adjusting data S0 and S1, each delay path is selectively activated to adjust the size (current drive capability) of the buffer circuit in the delayed clock generating circuit. Equivalently, the cascaded two inverter circuits each have sizes adjusted in accordance with the actual current drive capability of the output circuit.
However, in the case of changing the equivalent size of the inverter circuit, as for the input/output response characteristics, steep rising/falling characteristics can be implemented, but the response time does not greatly change, so that the delay time cannot be changed to a large extent (only the waveform of the delayed clock signal becomes steep or not). Therefore, it is impossible to adjust sufficiently and accurately the delay time of the delayed clock signal in accordance with the actual drive capability of the output circuit, and the delay time can be adjusted only within a narrow range due to restrictions by the response time of the inverter buffer. This results in a problem that the adjusting margin of the slew rate is small.
An object of the present invention is to provide a slew rate adjusting circuit and a semiconductor device, which allow accurate adjustment of the output slew rate.
Another object of the present invention is to provide a slew rate adjusting circuit and a semiconductor device, which allows change in slew rate over a sufficiently wide range of a delay time, without restrictions by a response time of an inverter circuit for producing a delayed clock signal.
A slew rate adjusting circuit according to the present invention includes a timing clock generating circuit for receiving a clock signal and producing an output timing signal. The timing clock generating circuit includes a variable delay circuit, having a number of delay stages variable, for delaying the clock signal.
The slew rate adjusting circuit according to the invention further includes a delay setting circuit for setting the number of the delay stages of the variable delay circuit according to slew rate adjusting data. An output circuit is activated in accordance with a timing clock signal, and drives an output node to produce external data in accordance with an internal data.
A semiconductor device according to the present invention includes: a timing clock producing circuit for receiving a clock signal and producing a first output timing signal; and an adjusted clock producing circuit for receiving the clock signal, and producing a second output timing signal delayed relative to the first output timing signal. The adjusted clock producing circuit includes a variable delay circuit having the number of delay stages variable.
The semiconductor device according to the invention further includes: a first output stage activated in accordance with the first output timing signal to drive an output node in accordance with an internal data; a second output stage being in accordance with the second output timing signal to drive the output node in accordance with the internal data; and a delay setting circuit for setting the number of delay stages of the variable delay circuit in accordance with slew rate adjusting data.
The variable delay circuit is used to produce the delayed clock signal (timing signal) for driving the output node. Thus, even in the case where the variable delay circuit is formed of inverter circuits, the delay time can be adjusted to a large extent by varying the number of delay stages independently of the input/output response characteristics of the inverter circuit. Consequently, a slew rate adjusting margin can be increased, and the output slew rate can be accurately adjusted in accordance with the actual output node drive capability of the output circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.